Search - sound with vhdl

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

Description: lattice sdram 控制器VHDL源代码-Sound code of Lattice Sdram Controller based on VHDL
Platform: | Size: 180224 | Author: 刘汉忠 | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
Platform: | Size: 425984 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilog] pingball

Description: 这是一个带声音的弹球小游戏，通过VGA口显示，通过扩展口JA的 pin4和 pin GND输出声音， BTN3 BTN2 控制挡板左右移动，弹球和挡板都自带动画效果-This is a band sound pinball game, through the VGA port shows that through the expansion of the mouth of the JA and pin4 output pin GND voice, BTN3 BTN2 control baffle around Mobile, pinball and baffle all bring their own animation effects
Platform: | Size: 1126400 | Author: 瑞 | Hits:

[VHDL-FPGA-Verilog] ima_adpcm_encoder_latest.tar

Description: This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
Platform: | Size: 23552 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] sopc

Description: 基于FPGA的SD卡音频播放器经过调试可以直接用，音质很好有MP3的所有功能-FPGA-based audio player, SD card can be directly used after debugging, good sound quality with all the features of MP3
Platform: | Size: 3476480 | Author: JHON | Hits:

[VHDL-FPGA-Verilog] digital_frequence_counter

Description: 设计功能： 1．.用VHDL完成12位十进制数字频率计的设计及仿真。 2．频率测量范围：1Hz∼ 10KHz，分成两个频段，即1∼ 999Hz，1KHz∼ 10KHz，用三位数码管显示测量频率，用LED显示表示单位，如亮绿灯表示Hz，亮红灯表示KHz。 3．具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。 4．具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -Design features: 1. . Complete with VHDL 12-bit decimal digital frequency meter design and simulation. 2. Frequency Range: 1Hz ~ 10KHz, divided into two bands, namely, 1 ~ 999Hz, 1KHz ~ 10KHz, with three digital display measuring frequency, with LED display that unit, such as the green light that Hz, red light, said KHz. 3. Calibration and measurement with automatic two functions, namely, the clock can use the standard calibration, measurement accuracy. 4. Super-range alarm function, beyond the scope of the present range of measurement files, the issue of light and sound signals.
Platform: | Size: 22528 | Author: 八毛 | Hits:

[VHDL-FPGA-Verilog] Marquee

Description: VHDL语言设计的跑马灯程序，使用8段数码管，并能递减计时，计时时间到蜂鸣器响声输出，数据在数码管上滚动显示，在试验箱上测试通过。-Marquee VHDL language design process, with 8 of the digital control, and can decrease time, time time to sound the buzzer output, data on the digital scroll in the chamber on the test.
Platform: | Size: 2048 | Author: 李志强 | Hits:

[VHDL-FPGA-Verilog] siluqiangdaqi

Description: 通过VHDL程序设计一个4人参加的智力竞赛抢答计时器，当有某一参赛者首先按下抢答开关时，相应显示灯亮并伴有声响，此时抢答器不再接受其他输入信号。电路具有回答问题时间控制功能。要求回答问题时间小于等于100s(显示为0~99)，时间显示采用倒计时方式。当达到限定时间时，发出声响以示警告。 -VHDL programming by a 4 quiz participants answer in timer, when a participant first press the answer in the switch, the corresponding display lights and accompanied by sound, then Responder no longer accept other input signals. Time control circuit has functions to answer questions. Required to answer questions in less than equal to 100s (shown as 0 to 99), with the countdown time display mode. When the time limit is reached, audible as a warning.
Platform: | Size: 6144 | Author: longking | Hits:

[VHDL-FPGA-Verilog] pingball

Description: 带声音的弹球小游戏,课余设计，使用VHDL-Pinball game with sound
Platform: | Size: 1128448 | Author: wenjia | Hits:

[Other] shuzipinlvji

Description: 1.用VHDL完成12位十进制数字频率计的设计及仿真。 2.频率测量范围：1Hz～10KHz，分成两个频段，即1～999Hz，1KHz～10KHz，用三位数码管显示测量频率，用LED显示表示单位，如亮绿灯表示Hz，亮红灯表示KHz。 3.具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。 4.具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -1 completed 12 with VHDL design and simulation of decimal digits of frequency. 2 Frequency Measurement Range:. 1Hz ~ 10KHz, divided into two bands, namely 1 ~ 999Hz, 1KHz ~ 10KHz, with three digital display measuring frequency, with LED display indicates the unit, such as a green light indicates Hz, red indicates KHz . 3 with automatic calibration and measurement two functions, namely, use standard clock calibration, measurement accuracy. 4 with over-range alarm function, when beyond the current range for the measurement range, emit light and sound signals.
Platform: | Size: 312320 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] music_player

Description: 音乐播放器，各模块使用VHDL写的，拥有暂停功能。jishu模块根据时钟信号产生八位递增的地址信号，传到music模块。music模块存放音乐的数据，根据得到的地址输出音阶。tonetab接收到音阶信号后会输出当前的音阶是多少，是否为高八度，用于数码管显示，同时将此音阶需要的分频率传给speaker模块。speaker模块根据接受到的分频比对2M的时钟进行分频，然后送给蜂鸣器发出声音。-Music player, each module written in VHDL, with pause function. jishu module generates eight incremented address signal according to the clock signal, transmitted music module. music module storing music data, based on the obtained address output scale. will scale the output signal is received after tonetab current scale is how much is a high octave, for digital display, while the frequency of this scale needs to pass the sub speaker module. speaker module in accordance with the received frequency-dividing the frequency dividing ratio of the clock 2M, and then sent to the buzzer sound.
Platform: | Size: 1419264 | Author: 马梁 | Hits:

[Other] Digital-frequency-meter

Description: 数字频率计:1.用VHDL完成12位十进制数字频率计的设计及仿真。 2.具有自动校验和测量两种功能。 3.具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -Digital frequency meter: 1 with 12 complete VHDL design and simulation decimal frequency meter. 2. With automatic calibration and measurement two functions. 3. With over-range alarm function when beyond the current range for the measuring range, emit light and sound signals.
Platform: | Size: 10240 | Author: 满文彦 | Hits:

[VHDL-FPGA-Verilog] digital-frequency-meter

Description: 1.用VHDL完成12位十进制数字频率计的设计及仿真。 2.频率测量范围：1Hz∼ 10KHz，分成两个频段，即1∼ 999Hz，1KHz∼ 10KHz，用三位数码管显示测量频率，用LED显示表示单位，如亮绿灯表示Hz，亮红灯表示KHz。 3.具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。 4.具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -1. VHDL design and simulation completed 12 decimal digits frequency meter. 2. Frequency measuring range: 1Hz~10KHz, divided into two bands, namely 1~999Hz, 1KHz~10KHz, with three digital display of measured frequency, with LED display showing the unit, such as a green light indicates Hz, red indicates KHz . 3. With automatic calibration and measurement two functions that use standard clock calibration, measurement accuracy. 4. With over-range alarm function when beyond the current range for the measuring range, emit light and sound signals.
Platform: | Size: 45056 | Author: 项小娇 | Hits:

[VHDL-FPGA-Verilog] VHDL-Multi-fuction-Clock

Description: 设计一个多功能数字钟，要求显示格式为小时－分钟－秒钟，整点报时，报时时间为10 秒，即从整点前10 秒钟开始进行报时提示，喇叭开始发声，直到过整点时，在整点前5 秒LED 开始闪烁，过整点后，停止闪烁。系统时钟选择时钟模块的10KHz，要得到1Hz 时钟信号，必须对系统时钟进行10,000次分频。调整时间的的按键用按键模块的S1 和S2，S1 调节小时，每按下一次，小时增加一个小时，S2 调整分钟，每按下一次，分钟增加一分钟。另外用S8 按键作为系统时钟复位，复位后全部显示00－00－00。-The design of a multi-function digital clock, required to display format for hours: Minutes: seconds, the whole point timekeeping and timer for 10 seconds, namely the whole point of 10 seconds before start timekeeping prompt, horn began to sound, until the whole point, in the whole point of 5 seconds the LED flashes, over the whole point, stop flicker. System clock to the clock module 10KHz, to get the 1Hz clock signal, the system must be 10000 times the system clock. Adjust the time of the keys with the key module S1 and S2, S1 adjust the hours, each press once, an hour to increase an hour, S2 to adjust the minutes, every time you press a minute, a minute. We also use the S8 button as the system clock reset, reset all display 00-00-00.
Platform: | Size: 7658496 | Author: 冯雨娴 | Hits:

[SCM] beep

Description: 用VHDL语言实现的蜂鸣器发声程序，当按下不同按键时，发出不同频率的声音(Function:when different buttens are pressed, beep will play sound with different frequency. laguage:VHDL)
Platform: | Size: 244736 | Author: panda_bupt | Hits:

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[VHDL-FPGA-Verilog] sdram_vhdl_lattice

[VHDL-FPGA-Verilog] DCT

[VHDL-FPGA-Verilog] shuzizhong

[VHDL-FPGA-Verilog] pingball

[VHDL-FPGA-Verilog] ima_adpcm_encoder_latest.tar

[VHDL-FPGA-Verilog] sopc

[VHDL-FPGA-Verilog] digital_frequence_counter

[VHDL-FPGA-Verilog] Marquee

[VHDL-FPGA-Verilog] siluqiangdaqi

[VHDL-FPGA-Verilog] pingball

[Other] shuzipinlvji

[VHDL-FPGA-Verilog] music_player

[Other] Digital-frequency-meter

[VHDL-FPGA-Verilog] digital-frequency-meter

[VHDL-FPGA-Verilog] VHDL-Multi-fuction-Clock

[SCM] beep

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